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PI6C106
Pentium/ProTM System Clock Chip
Features
* Three CPUs @2.5V, up to 100 MHz * Seven PCIs @ 3.3V (including one free running, 1 early) * One 48 MHz @ 3.3V fixed * One REF (3.3V, 14.318 MHz) * One IOAPIC (2.5V, 14.318 MHz) * Strong REF clock (1V/ns @50pF load) * Excellent power management features including Power Down, PCI, and CPU stops * Spread Spectrum for EMI control (0.5% down spread) * Early PCI (2.5ns 700ps) * Enhanced PCICLK4 (1.5X) * 28-pin SSOP Packaging (H)
Description
The PI6C106 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are PI6C182 & PI6C184. There are two PLLs, with the first PLL capable of spread spectum operation. CPU frequencies up to 100 MHz are supported.
Frequency Table
SEL 100/66.6# 1 0 CPU M Hz 100 66.6 PCI M Hz 33.3 33.3
Block Diagram
Pin Configuration
GND1
X1 X2 OSC REF0 VDDLA IOAPIC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
REF0 VDD1 IOAPIC VDDLA CPUCLK0 CPUCLK1 CPUCLK2 VDDLC GND PCI_STOP# CPU_STOP# PD# SPREAD# GND3
X1 X2 GND2 PCICLK_E
CPU_STOP# SPREAD# VDDLC PLL Spread Spectrum CPU STOP CPUCLK(0:2)
PCICLK_F PCICLK0
SEL 100/66.6#
/2 PD#
/3
PCICLK1 VDD2
PCICLK_E
28-Pin H
22 21 20 19 18 17 16 15
BUS STOP#
PCICLK2
PCICLK(0:4)
PCICLK3
PCICLK_F PCI_STOP# PLL2 48MHz
PCICLK4/ SEL100/66.6# VDD3 48MHz
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PI6C106 Pentium/ProTM System Clock Chip
Pin Descriptions
Pin Numbe r 1 2 3 4 5 6 7,8,10,11 9 12 13 14 15 16 17 18 19 20 21 22,23,24 25 26 27 28 Pin Name GND1 X1 X2 GND2 PCICLK _E PCICLK _F PCICLK (0:3) VDD2 PCICLK_4 SEL100/66.6# VDD3 48 MHz GND3 SPREAD# PD# CPU_STO P# PCI_STO P# GND VDDLC CPUCLK (2:0) VDDLA IO APIC VDD1 REF0 Type PWR IN O UT PWR OUT OUT O UT PWR O UT IN PWR O UT PWR IN IN IN IN PWR PWR OUT PWR OUT PWR OUT Ground for REF output, X1, X2. XTAL_IN 14.318 MHz Crystal input, has internal 33pF load cap and feedback resistor from X2. XTAL_O UT Crystal outut, has internal load cap 33pF Ground for PCI outputs Early PCICLK . Leads PCICLK(0:4,_F) by 2ns 250ps. Not affected by PCI_STO P#. Free Running PCI output. Not affected by PCI_STOP#. PCI clock outputs. TTL compatible 3.3V. Power for PCICLK outputs, nominally 3.3V. PCI clock output. TTL compatible 3.3V. (1.5X) Select pin for enabling 100MHz or 66.6 MHz. H=100 MHz, L=66.6 MHz (PCI always synchronous 33.3 MHz). Power for 48 MHz. Fixed CLK output @ 48 MHz. Ground for 48 MHz. Turns on Spread Spectrum when active. 0.5% down spread 0.1. Powers down chip. Internal PLLs, all output are turned off. Halts CPUCLK (2:0) at logic "0" level when input is low. Halts CPUCLK (0:4) at logic "0" level when input is low. Does not affect PCICLK_E and PCICLK _F Ground for PLL core. Power for CPU outputs, nominally 2.5V CPU and Host clock outputs nominally 2.5V Power for IOAPIC. IO APIC clock output 14.318MHz. Power for REF outputs. 14.318 MHz clock output. D e s cription
Note: Inactive means outputs are held LOW and are disabled from switching
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Pentium/Pro
TM
PI6C106 System Clock Chip
CPU_STOP# Timing Diagram
CPUS_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Internal CPUCLK
PCICLK (0:4) CPU_STOP# PCI_STOP# (HIGH) PD# (HIGH) CPUCLK (0:2)
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside PI6C106. 3. All other clocks continue to run undisturbed including SDRAMR. 4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the PI6C106. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the PI6C106 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Internal CPUCLK
Internal PCICLK
PCICLK (free-runningl) CPU_STOP#
PCI_STOP# PWR_DWN#
PCICLK (external)
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the PI6C106. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
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PI6C106 Pentium/ProTM System Clock Chip
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internal by the PI6C106 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations.
CPUCLK (Internal)
PCICLK (Internal) PD#
CPUCLK (0:2) PCICLK_E, PCICLK_F, PCICLK (0:4)
REF, IOAPIC INTERNAL VCOs INTERNAL CRYSTAL OSC.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the PI6C106. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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Pentium/Pro
TM
PI6C106 System Clock Chip
Absolute Maximum Ratings
Supply Voltage ........................................................... 7.0 V Logic Inputs ...............................GND 0.5 V to VDD +0.5 V Ambient Operating Temperature .................. 0C to +70C Storage Temperature ................................ 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings arestress specifications only and functional operation of the device at these or any other conditions above those listed in theoperational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periodsmay affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0C - 70C; Supply Voltage VDD = VDDL = 3.3 V 5% (unless otherwise stated).
Parame te r Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input Frequency Input Capacitance(1) Transition Time(1) Settling Time(1) Clock Stabilization(1)
Symbol VIH VIL IIH IIL1 IIL2 IDD3.3OP Fi CIN CINX Ttrans TS TSTAB VIN = VDD
Conditions
M in. 2 VSS0.3
Typ.
M ax. VDD+0.3 0.8 5
Units V
VIN = 0V; Inputs with no pull- up resistors VIN = 0V; Inputs with pull- up resistors CL = 0pF; 66.6 MHz CL = 0pF; 100 MHz VDD = 3.3V Logic Inputs X1 & X2 pins To first crossing to 1% target frequency From first crossing to 1% target frequency From VDD = 3.3V to 1% target frequency
5 200 100 100 12 27 16 5 45 3 2 3
A
mA MHz pF
ms
Electrical Characteristics - Input/Supply/Common Output Parameters
Parame te r Operating Supply Current Symbol IDD2.5OP Conditions CL = 0pF; 66.8 MHz CL = 0pF; 100 MHz Power Down Current Skew(1) IDD2.5OP TCPU_PCI(F,0:4) TPCI(E) - PCIC(F) VT = 1.5V / 1.25V; CPU Leads VT = 1.5V
TA = 0C - 70C; Supply Voltage VDD = 3.3 V 5%, VDDL = 2.5V 5% (unless otherwise stated).
M in.
Typ.
M ax. 50 50 100
Units mA A ns
1.5 1.8
4 3.2
Note: 1. Guaranteed by design, not 100% tested in production.
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PI6C106 Pentium/ProTM System Clock Chip
Electrical Characteristics - CPU
Parame te r O utput High Voltage Output Low Voltage O utput High Current O utput Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Single Edge Displacement(2) Jitter, O ne Sigma jitter, Absolute
TA = 0C - 70C; VDD = 3.3V 5%, VDDL = 2.5V 5%; CL = 10-20pF (unless otherwise stated).
Symbol VOH VOL IOH IOL tr tf dt tsk tjsed tj1 tjabs
Conditions IOH = 12mA IOL = 12mA VOH = 1.7V VOL = 0.7V VOL = 0.4V, VOH = 2.0V VOH = 2.0V, VOL = 0.4V VT = 1.25V VT = 1.25V VT = 1.25V VT = 1.25V VT = 1.25V
M in. 2
Typ.
M ax. 0.4 16
Units V mA ns %
19 1.6 1.6 45 55 175 250 150 300 300
ps
Notes: 1. Guaranteed by design, not 100% tested in production. 2. Edge displacement of a period relative to a 10-clock-cycle rolling average period
Electrical Characteristics - PCI
Parame te r Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Single Edge Displacement(2) jitter, Absolute
TA = 0C - 70C; VDD = VDDL = 3.3V 10%, CL = 30pF (unless otherwise stated).
Symbol VOH1 VOL1 IOH1 IOL1 tr tf dt tsk tjsed tjabs
Conditions IOH = 11mA IOL = 9.4mA VOH = 2.0V VOL = 0.8V VOL = 0.4V, VOH = 2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V VT = 1.25V VT = 1.5V VT = 1.5V
M in. 2.6
Typ.
M ax. 0.4 22
Units V mA ns %
16 2 2 45 55 500 500 250 200 250
ps
Notes: 1. Guaranteed by design, not 100% tested in production.
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Pentium/Pro
TM
PI6C106 System Clock Chip
Electrical Characteristics - REF0
Parame te r O utput High Voltage O utput Low Voltage O utput High Current O utput Low Current Rise Time Fall Time Duty Cycle Jitter, O ne Sigma Jitter, Absolute
TA = 0C - 70C; VDD = VDDL = 3.3V 10%, CL = 50pF (unless otherwise stated).
Symbol VOH VOL IOH IOL tr tf(1) dt tj1s tjabs
Conditions IOH = 12mA IOL = 9mA VOH = 2.0V VOL = 0.8V VOL = 0.4V, VOH = 2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V VT = 1.5V
M in. 2.6
Typ.
M ax. 0.4 22
Units V mA ns % ns
16 2 2 53 5 55 3 5
Electrical Characteristics - IOAPIC
Parame te r O utput High Voltage O utput Low Voltage O utput High Current O utput Low Current Rise Time Fall Time Duty Cycle Jitter, O ne Sigma(1) Jitter, Absolute(1)
TA = 0C - 70C; VDD = VDDL = 3.3V 10%, CL = 20pF (unless otherwise stated).
Symbol VOH VOL IOH IOL tr2 tf2 dt2 tj1s tjabs
Conditions IOH = 12mA IOL = 12mA VOH = 1.7V VOL = 0.7V VOL = 0.4V, VOH = 2.0V VOH = 2.0V, VOL = 0.4V VT = 1.25V VT = 1.5V VT = 1.5V
M in. 2.0
Typ.
M ax. 0.4 16
Units V mA ns % ns
19 1.6 1.6 45 6 55 3 6
Electrical Characteristics - 48M
Parame te r O utput High Voltage O utput Low Voltage O utput High Current O utput Low Current Rise Time Fall Time Duty Cycle(1) Jitter, O ne Sigma(1) Jitter, Absolute(1)
TA = 0C - 70C; VDD = VDDL = 3.3V 5%, CL = 20pF (unless otherwise stated).
Symbol VOH VOL IOH IOL tr tf dt tj1s tjabs
Conditions IOH = 11mA IOL = 9.4mA VOH = 2.0V VOL = 0.8V VOL = 0.4V, VOH = 2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V VT = 1.5V
M in. 2.4
Typ.
M ax. 0.4 18
Units V mA ns % ns
12 2.5 2.5 45 6 55 3 6
Note: 1. Guaranteed by design, not 100% tested in production.
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PI6C106 Pentium/ProTM System Clock Chip
28-Pin SSOP Package (H)
Ordering Information
Part No. PI6C106 Package SSO P (H- 28) Orde ring P/N PI6C106- H
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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